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�0u~��x��{��~@������������x�������� ���0���������������8������|�$���������l��������.���������D�H���f���h�\��t���X�<���:���$������L�������x��H������d�0 D�t%��+���/���4��49���=���B��Fz�K�,P��V���[0�b�g&�<l,�hp��u���y��\~���������<���Ĉ��*������������x�h��������MUI����T�P?����^���P��R��f�%-l�����MUIen-USHV Host Service|Provides an interface for the Hyper-V hypervisor to provide per-partition performance counters to the host operating system.PAHyper-V HypervisorHyper-V HypervisorInformation on the hypervisor.Logical ProcessorsLogical Processors7The number of logical processors present in the system.
Partitions
PartitionsBThe number of partitions (virtual machines) present in the system.Total PagesTotal Pages>The number of bootstrap and deposited pages in the hypervisor.PAVirtual ProcessorsVirtual Processors7The number of virtual processors present in the system.Monitored NotificationsMonitored NotificationsEThe number of monitored notifications registered with the hypervisor.Modern Standby EntriesModern Standby EntriesDThe number of modern/connected standby entry notifications received.Platform Idle TransitionsPlatform Idle Transitions(The number of platform idle transitions.HypervisorStartupCostHypervisorStartupCost9Cycles for Hypervisor Startup on the bootstrap processor.IO Space PagesIO Space Pages/The number of I/O space pages in the hypervisorNonEssentialPagesForDumpNonEssentialPagesForDump?The number of deposited pages that can be excluded from a dump.$Hyper-V Hypervisor Logical Processor$Hyper-V Hypervisor Logical Processor"Information on logical processors.PAGlobal TimeGlobal Time*The global time on this logical processor.Total Run TimeTotal Run TimeNThe total time (in 100ns) spent by the processor in guest and hypervisor code.Hypervisor Run TimeHypervisor Run TimeDThe total time (in 100ns) spent by the processor in hypervisor code.Hardware Interrupts/secHardware Interrupts/secSThe rate of hardware interrupts on the processor (excluding hypervisor interrupts).PAContext Switches/secContext Switches/sec@The rate of virtual processor context switches on the processor.Inter-Processor Interrupts/secInter-Processor Interrupts/secMThe rate of hypervisor inter-processor interrupts delivered to the processor.Scheduler Interrupts/secScheduler Interrupts/sec=The rate of hypervisor scheduler interrupts on the processor.Timer Interrupts/secTimer Interrupts/sec9The rate of hypervisor timer interrupts on the processor.PA#Inter-Processor Interrupts Sent/sec#Inter-Processor Interrupts Sent/secHThe rate of hypervisor inter-processor interrupts sent by the processor.Processor Halts/secProcessor Halts/sec7The rate of entries into a halt state by the processor.Monitor Transition CostMonitor Transition Cost5The hardware cost of transitions into the hypervisor.Context Switch TimeContext Switch TimeKThe total time (in nanoseconds) spent switching between virtual processors.PAC1 Transitions/secC1 Transitions/secKC1 Transitions/sec is the rate that CPU enters the C1 low-power idle state.	% C1 Time	% C1 Time�% C1 Time is the percentage of time the processor spends in the C1 low-power idle state. % C1 Time is a subset of the total processor idle time.C2 Transitions/secC2 Transitions/secKC2 Transitions/sec is the rate that CPU enters the C2 low-power idle state.	% C2 Time	% C2 Time�% C2 Time is the percentage of time the processor spends in the C2 low-power idle state. % C2 Time is a subset of the total processor idle time.C3 Transitions/secC3 Transitions/secKC3 Transitions/sec is the rate that CPU enters the C3 low-power idle state.	% C3 Time	% C3 Time�% C3 Time is the percentage of time the processor spends in the C3 low-power idle state. % C3 Time is a subset of the total processor idle time.	Frequency	FrequencyKProcessor Frequency is the frequency of the current processor in megahertz.% of Max Frequency% of Max FrequencyV% of Maximum Frequency is the percentage of the current processor's maximum frequency.Parking StatusParking Status?Parking Status represents whether a processor is parked or not.Processor State FlagsProcessor State FlagsProcessor State Flags
Root Vp Index
Root Vp Index�Index of the root virtual processor that is affinity bound to this logical processor.  A value that is greater than the maximum possible root VP index indicates no binding.Idle Sequence NumberIdle Sequence NumberIdle Sequence Number.PAGlobal TSC CountGlobal TSC Count.The Global TSC count on this logical processorActive TSC CountActive TSC Count6Counter that accumulates TSC counts for active periodsIdle AccumulationIdle Accumulation-Counter that accumulates idle time (in 100ns)Reference Cycle Count 0Reference Cycle Count 0EMonotonically increasing counter running at processor's nominal rate.Actual Cycle Count 0Actual Cycle Count 0DMonotonically increasing counter running at processor's actual rate.Reference Cycle Count 1Reference Cycle Count 1EMonotonically increasing counter running at processor's nominal rate.Actual Cycle Count 1Actual Cycle Count 1DMonotonically increasing counter running at processor's actual rate.Proximity Domain IdProximity Domain Id8Proximity Domain Id of the node to which the LP belongs.PA"Posted Interrupt Notifications/sec"Posted Interrupt Notifications/sec<The rate of posted interrupt notifications on the processor.'Hypervisor Branch Predictor Flushes/sec'Hypervisor Branch Predictor Flushes/sec0The rate of hypervisor branch predictor flushes.$Hypervisor L1 Data Cache Flushes/sec$Hypervisor L1 Data Cache Flushes/sec-The rate of hypervisor L1 data cache flushes..Hypervisor Immediate L1 Data Cache Flushes/sec.Hypervisor Immediate L1 Data Cache Flushes/sec7The rate of hypervisor immediate L1 data cache flushes.0Hypervisor Microarchitectural Buffer Flushes/sec0Hypervisor Microarchitectural Buffer Flushes/sec9The rate of hypervisor microarchitectural buffer flushes.Counter Refresh Sequence NumberCounter Refresh Sequence NumberVSequence number which is incremented when performance counter refresh begins and ends.Counter Refresh Reference TimeCounter Refresh Reference Time=Reference time when performance counters were last refreshed.Idle Accumulation SnapshotIdle Accumulation Snapshot_Counter that accumulates idle time (in 100ns). Updated when performance counters are refreshed.PAActive Tsc Count SnapshotActive Tsc Count SnapshothCounter that accumulates TSC counts for active periods. Updated when performance counters are refreshed.$HWP Request MSR Context Switches/sec$HWP Request MSR Context Switches/sec8The rate of hypervisor HWP_REQUEST MSR context switches.
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Placeholder 9Placeholder counter.Placeholder 10Placeholder 10Placeholder counter.Guest Run TimeGuest Run Time?The total time (in 100ns) spent by the processor in guest code.	Idle Time	Idle TimeBThe total time (in 100ns) spent by the processor in an idle state.% Total Run Time% Total Run TimeKThe percentage of time spent by the processor in guest and hypervisor code.% Hypervisor Run Time% Hypervisor Run TimeAThe percentage of time spent by the processor in hypervisor code.PA% Guest Run Time% Guest Run Time<The percentage of time spent by the processor in guest code.% Idle Time% Idle Time?The percentage of time spent by the processor in an idle state.Total Interrupts/secTotal Interrupts/sec3The rate of hardware and hypervisor interrupts/sec.Reserve Group IdReserve Group IdCThe Group ID that has reserved the LP as part of its Idle Reserves.PARunning PriorityRunning PriorityThe Running Priority of the LP.%Performance Monitoring Interrupts/sec%Performance Monitoring Interrupts/secRThe rate of performance monitoring interrupts encountered on this logical procesor!Hyper-V Hypervisor Root Partition!Hyper-V Hypervisor Root PartitionInformation on virtual machinesVirtual ProcessorsVirtual Processors:The number of virtual processors present in the partition.Virtual TLB PagesVirtual TLB Pages=The number of pages used by the virtual TLB of the partition.Address SpacesAddress SpacesAThe number of address spaces in the virtual TLB of the partition.Deposited PagesDeposited Pages1The number of pages deposited into the partition.	GPA Pages	GPA PagesXThe number of pages present in the GPA space of the partition (zero for root partition).PAGPA Space Modifications/secGPA Space Modifications/sec<The rate of modifications to the GPA space of the partition.Virtual TLB Flush Entires/secVirtual TLB Flush Entires/sec.The rate of flushes of the entire virtual TLB.Recommended Virtual TLB SizeRecommended Virtual TLB SizeDThe recommended number of pages to be deposited for the virtual TLB.4K GPA pages4K GPA pagesAThe number of 4K pages present in the GPA space of the partition.PA2M GPA pages2M GPA pagesAThe number of 2M pages present in the GPA space of the partition.1G GPA pages1G GPA pagesAThe number of 1G pages present in the GPA space of the partition.512G GPA pages512G GPA pagesCThe number of 512G pages present in the GPA space of the partition.4K device pages4K device pagesDThe number of 4K pages present in the device space of the partition.PA2M device pages2M device pagesDThe number of 2M pages present in the device space of the partition.1G device pages1G device pagesDThe number of 1G pages present in the device space of the partition.512G device pages512G device pagesFThe number of 512G pages present in the device space of the partition.Attached DevicesAttached Devices0The number of devices attached to the partition.Device Interrupt MappingsDevice Interrupt Mappings>The number of device interrupt mappings used by the partition.I/O TLB Flushes/secI/O TLB Flushes/sec1The rate of flushes of I/O TLBs of the partition.I/O TLB Flushes BaseI/O TLB Flushes Base9The total number of flushes of I/O TLBs of the partition.I/O TLB Flush CostI/O TLB Flush CostDThe average time (in nanoseconds) spent processing an I/O TLB flush.Device Interrupt ErrorsDevice Interrupt Errors^An indicator of illegal interrupt requests generated by all devices assigned to the partition.Device DMA ErrorsDevice DMA ErrorsXAn indicator of illegal DMA requests generated by all devices assigned to the partition. Device Interrupt Throttle Events Device Interrupt Throttle Events�The number of times an interrupt from a device assigned to the partition was temporarily throttled because the device was generating too many interrupts.Skipped Timer TicksSkipped Timer Ticks9The number of timer interrupts skipped for the partition.Partition IdPartition Id-The hypervisor partition ID for the partitionNested TLB SizeNested TLB Size1The number of pages deposited for the nested TLB.Recommended Nested TLB SizeRecommended Nested TLB SizeCThe recommended number of pages to be deposited for the nested TLB.Nested TLB Free List SizeNested TLB Free List Size+The number of free pages in the nested TLB.Nested TLB Trimmed Pages/secNested TLB Trimmed Pages/sec.The rate of pages trimmed from the nested TLB.Pages Shattered/secPages Shattered/secThe rate of pages shatteredPages Recombined/secPages Recombined/secThe rate of pages recombinedHWP Requested Performance LevelHWP Requested Performance Level2The effective HWP_REQUEST value for the partition.PA)Hyper-V Hypervisor Root Virtual Processor)Hyper-V Hypervisor Root Virtual Processor!Information on virtual processorsTotal Run TimeTotal Run TimeVThe total time (in 100ns) spent by the virtual processor in guest and hypervisor code.Hypervisor Run TimeHypervisor Run TimeLThe total time (in 100ns) spent by the virtual processor in hypervisor code.Remote Node Run TimeRemote Node Run Time4The time (in 100ns) spent running on remote node(s).PANormalized Run TimeNormalized Run TimetThe total time (in 100ns) spent by the virtual processor in guest and hypervisor code, normalized to peak frequency.Hypercalls/secHypercalls/secCThe rate of hypercalls made by guest code on the virtual processor.Hypercalls BaseHypercalls BaseKThe total number of hypercalls made by guest code on the virtual processor.Hypercalls CostHypercalls Cost?The average time (in nanoseconds) spent processing a hypercall.PAPage Invalidations/secPage Invalidations/secPThe rate of INVLPG instructions executed by guest code on the virtual processor.Page Invalidations BasePage Invalidations BaseXThe total number of INVLPG instructions executed by guest code on the virtual processor.Page Invalidations CostPage Invalidations CostIThe average time (in nanoseconds) spent processing an INVLPG instruction.Control Register Accesses/secControl Register Accesses/secMThe rate of control register accesses by guest code on the virtual processor.Control Register Accesses BaseControl Register Accesses BaseUThe total number of control register accesses by guest code on the virtual processor.Control Register Accesses CostControl Register Accesses CostMThe average time (in nanoseconds) spent processing a control register access.IO Instructions/secIO Instructions/secLThe rate of IO instructions executed by guest code on the virtual processor.IO Instructions BaseIO Instructions BaseTThe total number of IO instructions executed by guest code on the virtual processor.IO Instructions CostIO Instructions CostEThe average time (in nanoseconds) spent processing an IO instruction.HLT Instructions/secHLT Instructions/secMThe rate of HLT instructions executed by guest code on the virtual processor.HLT Instructions BaseHLT Instructions BaseUThe total number of HLT instructions executed by guest code on the virtual processor.HLT Instructions CostHLT Instructions CostEThe average time (in nanoseconds) spent processing a HLT instruction.MWAIT Instructions/secMWAIT Instructions/secOThe rate of MWAIT instructions executed by guest code on the virtual processor.MWAIT Instructions BaseMWAIT Instructions BaseWThe total number of MWAIT instructions executed by guest code on the virtual processor.MWAIT Instructions CostMWAIT Instructions CostHThe average time (in nanoseconds) spent processing an MWAIT instruction.CPUID Instructions/secCPUID Instructions/secOThe rate of CPUID instructions executed by guest code on the virtual processor.PACPUID Instructions BaseCPUID Instructions BaseWThe total number of CPUID instructions executed by guest code on the virtual processor.CPUID Instructions CostCPUID Instructions CostGThe average time (in nanoseconds) spent processing a CPUID instruction.MSR Accesses/secMSR Accesses/secMThe rate of MSR instructions executed by guest code on the virtual processor.MSR Accesses BaseMSR Accesses BaseLThe total number of MSR instructions by guest code on the virtual processor.PAMSR Accesses CostMSR Accesses CostFThe average time (in nanoseconds) spent processing an MSR instruction.Other Intercepts/secOther Intercepts/secNThe rate of other intercepts triggered by guest code on the virtual processor.Other Intercepts BaseOther Intercepts BaseVThe total number of other intercepts triggered by guest code on the virtual processor.Other Intercepts CostOther Intercepts CostDThe average time (in nanoseconds) spent processing other intercepts.External Interrupts/secExternal Interrupts/secoThe rate of external interrupts received by the hypervisor while executing guest code on the virtual processor.External Interrupts BaseExternal Interrupts BasewThe total number of external interrupts received by the hypervisor while executing guest code on the virtual processor.External Interrupts CostExternal Interrupts CostIThe average time (in nanoseconds) spent processing an external interrupt.Pending Interrupts/secPending Interrupts/seceThe rate of intercepts due to a task priority (TPR) reduction by guest code on the virtual processor.Pending Interrupts BasePending Interrupts BasemThe total number of intercepts due to a task priority (TPR) reduction by guest code on the virtual processor.Pending Interrupts CostPending Interrupts CostQThe average time (in nanoseconds) spent processing a pending interrupt intercept.Emulated Instructions/secEmulated Instructions/secVThe rate of emulated instructions while executing guest code on the virtual processor.Emulated Instructions BaseEmulated Instructions Base^The total number of emulated instructions while executing guest code on the virtual processor.Emulated Instructions CostEmulated Instructions CostAThe average time (in nanoseconds) spent emulating an instruction.Debug Register Accesses/secDebug Register Accesses/secKThe rate of debug register accesses by guest code on the virtual processor.Debug Register Accesses BaseDebug Register Accesses BaseSThe total number of debug register accesses by guest code on the virtual processor.Debug Register Accesses CostDebug Register Accesses CostIThe average time (in nanoseconds) spent handling a debug register access.Page Fault Intercepts/secPage Fault Intercepts/sectThe rate of page fault exceptions intercepted by the hypervisor while executing guest code on the virtual processor.Page Fault Intercepts BasePage Fault Intercepts Base|The total number of page fault exceptions intercepted by the hypervisor while executing guest code on the virtual processor.Page Fault Intercepts CostPage Fault Intercepts CostJThe average time (in nanoseconds) spent processing a page fault intercept.NMI Interrupts/secNMI Interrupts/secsThe rate of Non-maskable interrupts received by the hypervisor while executing guest code on the virtual processor.PANMI Interrupts BaseNMI Interrupts Base{The total number of Non-maskable interrupts received by the hypervisor while executing guest code on the virtual processor.NMI Interrupts CostNMI Interrupts CostLThe average time (in nanoseconds) spent processing a non-maskable interrupt.Guest Page Table Maps/secGuest Page Table Maps/sec6The rate of map operations for guest page table pages.Large Page TLB Fills/secLarge Page TLB Fills/sec.The rate of virtual TLB misses on large pages.PASmall Page TLB Fills/secSmall Page TLB Fills/sec+The rate of virtual TLB misses on 4K pages.Reflected Guest Page Faults/secReflected Guest Page Faults/sec9The rate of page fault exceptions delivered to the guest.APIC MMIO Accesses/secAPIC MMIO Accesses/secOThe rate of APIC MMIO register accesses by guest code on the virtual processor.IO Intercept Messages/secIO Intercept Messages/sec?The rate of IO intercept messages sent to the parent partition.Memory Intercept Messages/secMemory Intercept Messages/secCThe rate of memory intercept messages sent to the parent partition.APIC EOI Accesses/secAPIC EOI Accesses/secLThe rate of APIC EOI register writes by guest code on the virtual processor.Other Messages/secOther Messages/secBThe rate of other intercept messages sent to the parent partition.Page Table Allocations/secPage Table Allocations/sec6The rate of page table allocations in the virtual TLB.PA Logical Processor Migrations/sec Logical Processor Migrations/secQThe rate of migrations by the virtual processor to a different logical processor.Address Space Evictions/secAddress Space Evictions/sec7The rate of address space evictions in the virtual TLB.Address Space Switches/secAddress Space Switches/secJThe rate of address space switches by guest code on the virtual processor.Address Domain Flushes/secAddress Domain Flushes/secWThe rate of explicit flushes of the virtual TLB by guest code on the virtual processor.PAAddress Space Flushes/secAddress Space Flushes/secYThe rate of explicit flushes of one address space by guest code on the virtual processor.Global GVA Range Flushes/secGlobal GVA Range Flushes/secuThe rate of explicit flushes of a virtual address range in all address spaces by guest code on the virtual processor.Local Flushed GVA Ranges/secLocal Flushed GVA Ranges/sectThe rate of explicit flushes of a virtual address range in one address space by guest code on the virtual processor.Page Table Evictions/secPage Table Evictions/sec4The rate of page table evictions in the virtual TLB.Page Table Reclamations/secPage Table Reclamations/secHThe rate of reclamations of unreferenced page tables in the virtual TLB.Page Table Resets/secPage Table Resets/sec1The rate of page table resets in the virtual TLB.Page Table Validations/secPage Table Validations/secNThe rate of page table validations to remove stale entries in the virtual TLB.APIC TPR Accesses/secAPIC TPR Accesses/secEThe rate of APIC TPR accesses by guest code on the virtual processor.Page Table Write Intercepts/secPage Table Write Intercepts/secYThe rate of write intercepts on guest page tables by guest code on the virtual processor.Synthetic Interrupts/secSynthetic Interrupts/secDThe rate of synthetic interrupts delivered to the virtual processor.Virtual Interrupts/secVirtual Interrupts/sec[The rate of interrupts (including synthetic interrupts) delivered to the virtual processor.APIC IPIs Sent/secAPIC IPIs Sent/sec^The rate of APIC inter-processor interrupts (including to self) sent by the virtual processor.APIC Self IPIs Sent/secAPIC Self IPIs Sent/secDThe rate of APIC interrupts sent by the virtual processor to itself.GPA Space Hypercalls/secGPA Space Hypercalls/sec`The rate of Guest Physical Address Space hypercalls made by guest code on the virtual processor. Logical Processor Hypercalls/sec Logical Processor Hypercalls/secUThe rate of Logical Processor hypercalls made by guest code on the virtual processor.Long Spin Wait Hypercalls/secLong Spin Wait Hypercalls/secRThe rate of Long Spin Wait hypercalls made by guest code on the virtual processor.PAOther Hypercalls/secOther Hypercalls/secIThe rate of other hypercalls made by guest code on the virtual processor."Synthetic Interrupt Hypercalls/sec"Synthetic Interrupt Hypercalls/secWThe rate of Synthetic Interrupt hypercalls made by guest code on the virtual processor. Virtual Interrupt Hypercalls/sec Virtual Interrupt Hypercalls/secUThe rate of Virtual Interrupt hypercalls made by guest code on the virtual processor.Virtual MMU Hypercalls/secVirtual MMU Hypercalls/secOThe rate of Virtual MMU hypercalls made by guest code on the virtual processor. Virtual Processor Hypercalls/sec Virtual Processor Hypercalls/secUThe rate of Virtual Processor hypercalls made by guest code on the virtual processor.Hardware Interrupts/secHardware Interrupts/secOThe rate of hardware interrupts from attached devices on the virtual processor. Nested Page Fault Intercepts/sec Nested Page Fault Intercepts/secsThe rate of nested page fault exceptions intercepted by the hypervisor while executing the guest virtual processor.!Nested Page Fault Intercepts Base!Nested Page Fault Intercepts BaseuThe total number of nested page fault exceptions intercepted by the hypervisor while executing the virtual processor.!Nested Page Fault Intercepts Cost!Nested Page Fault Intercepts CostQThe average time (in nanoseconds) spent processing a nested page fault intercept.Page Scans/secPage Scans/secThe rate of page scans Logical Processor Dispatches/sec Logical Processor Dispatches/secIThe rate of dispatches of this virtual processor onto logical processors.!Logical Processor Dispatches Base!Logical Processor Dispatches BaseQThe total number of dispatches of this virtual processor onto logical processors.PACPU Wait Time Per DispatchCPU Wait Time Per DispatchrThe average time (in nanoseconds) spent waiting for a virtual processor to be dispatched onto a logical processor.Extended Hypercalls/secExtended Hypercalls/secNThe number of extended hypercalls made by guest code on the virtual processor.)Extended Hypercall Intercept Messages/sec)Extended Hypercall Intercept Messages/secJThe rate of extended hypercall intercept messages to the parent partition.#MBEC Nested Page Table Switches/sec#MBEC Nested Page Table Switches/sec�The rate of nested page table switches for mode based execution that the hypervisor initiated while executing the guest virtual processor.$Other Reflected Guest Exceptions/sec$Other Reflected Guest Exceptions/sec=The rate of non-page fault exceptions delivered to the guest.Global I/O TLB Flushes/secGlobal I/O TLB Flushes/secMThe rate of flushes of I/O TLBs for all PASIDs made by the virtual processor.Global I/O TLB Flushes BaseGlobal I/O TLB Flushes BaseUThe total number of flushes of I/O TLBs for all PASIDs made by the virtual processor.Global I/O TLB Flush CostGlobal I/O TLB Flush CostJThe average time (in nanoseconds) spent processing a global I/O TLB flush.PALocal I/O TLB Flushes/secLocal I/O TLB Flushes/secLThe rate of flushes of I/O TLBs for one PASID made by the virtual processor.Local I/O TLB Flushes BaseLocal I/O TLB Flushes BaseTThe total number of flushes of I/O TLBs for one PASID made by the virtual processor.Local I/O TLB Flush CostLocal I/O TLB Flush CostIThe average time (in nanoseconds) spent processing a local I/O TLB flush.Hypercalls Forwarded/secHypercalls Forwarded/secSThe rate of hypercalls forwarded to the nested hypervisor on the virtual processor.Hypercalls Forwarded BaseHypercalls Forwarded Base[The total number of hypercalls forwarded to the nested hypervisor on the virtual processor.Hypercalls Forwarding CostHypercalls Forwarding Cost?The average time (in nanoseconds) spent forwarding a hypercall. Page Invalidations Forwarded/sec Page Invalidations Forwarded/sec\The rate of INVLPG instructions forwarded to the nested hypervisor on the virtual processor.!Page Invalidations Forwarded Base!Page Invalidations Forwarded BasedThe total number of INVLPG instructions forwarded to the nested hypervisor on the virtual processor."Page Invalidations Forwarding Cost"Page Invalidations Forwarding CostIThe average time (in nanoseconds) spent forwarding an INVLPG instruction.'Control Register Accesses Forwarded/sec'Control Register Accesses Forwarded/secbThe rate of control register accesses forwarded to the nested hypervisor on the virtual processor.(Control Register Accesses Forwarded Base(Control Register Accesses Forwarded BasejThe total number of control register accesses forwarded to the nested hypervisor on the virtual processor.)Control Register Accesses Forwarding Cost)Control Register Accesses Forwarding CostMThe average time (in nanoseconds) spent forwarding a control register access.IO Instructions Forwarded/secIO Instructions Forwarded/secXThe rate of IO instructions forwarded to the nested hypervisor on the virtual processor.IO Instructions Forwarded BaseIO Instructions Forwarded Base`The total number of IO instructions forwarded to the nested hypervisor on the virtual processor.IO Instructions Forwarding CostIO Instructions Forwarding CostEThe average time (in nanoseconds) spent forwarding an IO instruction.HLT Instructions Forwarded/secHLT Instructions Forwarded/secYThe rate of HLT instructions forwarded to the nested hypervisor on the virtual processor.HLT Instructions Forwarded BaseHLT Instructions Forwarded BaseaThe total number of HLT instructions forwarded to the nested hypervisor on the virtual processor. HLT Instructions Forwarding Cost HLT Instructions Forwarding CostEThe average time (in nanoseconds) spent forwarding a HLT instruction. MWAIT Instructions Forwarded/sec MWAIT Instructions Forwarded/sec[The rate of MWAIT instructions forwarded to the nested hypervisor on the virtual processor.!MWAIT Instructions Forwarded Base!MWAIT Instructions Forwarded BasecThe total number of MWAIT instructions forwarded to the nested hypervisor on the virtual processor."MWAIT Instructions Forwarding Cost"MWAIT Instructions Forwarding CostHThe average time (in nanoseconds) spent forwarding an MWAIT instruction. CPUID Instructions Forwarded/sec CPUID Instructions Forwarded/sec[The rate of CPUID instructions forwarded to the nested hypervisor on the virtual processor.!CPUID Instructions Forwarded Base!CPUID Instructions Forwarded BasecThe total number of CPUID instructions forwarded to the nested hypervisor on the virtual processor."CPUID Instructions Forwarding Cost"CPUID Instructions Forwarding CostGThe average time (in nanoseconds) spent forwarding a CPUID instruction.PAMSR Accesses Forwarded/secMSR Accesses Forwarded/secYThe rate of MSR instructions forwarded to the nested hypervisor on the virtual processor.MSR Accesses Forwarded BaseMSR Accesses Forwarded BaseaThe total number of MSR instructions forwarded to the nested hypervisor on the virtual processor.MSR Accesses Forwarding CostMSR Accesses Forwarding CostFThe average time (in nanoseconds) spent forwarding an MSR instruction.Other Intercepts Forwarded/secOther Intercepts Forwarded/secYThe rate of other intercepts forwarded to the nested hypervisor on the virtual processor.PAOther Intercepts Forwarded BaseOther Intercepts Forwarded BaseaThe total number of other intercepts forwarded to the nested hypervisor on the virtual processor. Other Intercepts Forwarding Cost Other Intercepts Forwarding CostDThe average time (in nanoseconds) spent forwarding other intercepts.!External Interrupts Forwarded/sec!External Interrupts Forwarded/sec\The rate of external interrupts forwarded to the nested hypervisor on the virtual processor."External Interrupts Forwarded Base"External Interrupts Forwarded BasedThe total number of external interrupts forwarded to the nested hypervisor on the virtual processor.PA#External Interrupts Forwarding Cost#External Interrupts Forwarding CostIThe average time (in nanoseconds) spent forwarding an external interrupt. Pending Interrupts Forwarded/sec Pending Interrupts Forwarded/seczThe rate of intercepts due to a task priority (TPR) reduction forwarded to the nested hypervisor on the virtual processor.!Pending Interrupts Forwarded Base!Pending Interrupts Forwarded Base�The total number of intercepts due to a task priority (TPR) reduction forwarded to the nested hypervisor on the virtual processor."Pending Interrupts Forwarding Cost"Pending Interrupts Forwarding CostQThe average time (in nanoseconds) spent forwarding a pending interrupt intercept.#Emulated Instructions Forwarded/sec#Emulated Instructions Forwarded/sec^The rate of emulated instructions forwarded to the nested hypervisor on the virtual processor.$Emulated Instructions Forwarded Base$Emulated Instructions Forwarded BasefThe total number of emulated instructions forwarded to the nested hypervisor on the virtual processor.%Emulated Instructions Forwarding Cost%Emulated Instructions Forwarding CostLThe average time (in nanoseconds) spent forwareding an emulated instruction.%Debug Register Accesses Forwarded/sec%Debug Register Accesses Forwarded/sec`The rate of debug register accesses forwarded to the nested hypervisor on the virtual processor.&Debug Register Accesses Forwarded Base&Debug Register Accesses Forwarded BasehThe total number of debug register accesses forwarded to the nested hypervisor on the virtual processor.'Debug Register Accesses Forwarding Cost'Debug Register Accesses Forwarding CostKThe average time (in nanoseconds) spent forwarding a debug register access.#Page Fault Intercepts Forwarded/sec#Page Fault Intercepts Forwarded/secyThe rate of page fault exceptions forwarded to the nested hypervisor while executing guest code on the virtual processor.$Page Fault Intercepts Forwarded Base$Page Fault Intercepts Forwarded BasefThe total number of page fault exceptions forwarded to the nested hypervisor on the virtual processor.%Page Fault Intercepts Forwarding Cost%Page Fault Intercepts Forwarding CostJThe average time (in nanoseconds) spent forwarding a page fault intercept. VMCLEAR Emulation Intercepts/sec VMCLEAR Emulation Intercepts/sec^The rate of VMCLEAR instructions emulated while executing guest code on the virtual processor.!VMCLEAR Emulation Intercepts Base!VMCLEAR Emulation Intercepts BaseKThe total number of VMCLEAR instructions emulated on the virtual processor."VMCLEAR Instruction Emulation Cost"VMCLEAR Instruction Emulation CostJThe average time (in nanoseconds) spent enumulating a VMCLEAR instruction.PA VMPTRLD Emulation Intercepts/sec VMPTRLD Emulation Intercepts/sec^The rate of VMPTRLD instructions emulated while executing guest code on the virtual processor.!VMPTRLD Emulation Intercepts Base!VMPTRLD Emulation Intercepts BaseKThe total number of VMPTRLD instructions emulated on the virtual processor."VMPTRLD Instruction Emulation Cost"VMPTRLD Instruction Emulation CostJThe average time (in nanoseconds) spent enumulating a VMPTRLD instruction. VMPTRST Emulation Intercepts/sec VMPTRST Emulation Intercepts/sec^The rate of VMPTRST instructions emulated while executing guest code on the virtual processor.PA!VMPTRST Emulation Intercepts Base!VMPTRST Emulation Intercepts BaseKThe total number of VMPTRST instructions emulated on the virtual processor."VMPTRST Instruction Emulation Cost"VMPTRST Instruction Emulation CostJThe average time (in nanoseconds) spent enumulating a VMPTRST instruction.VMREAD Emulation Intercepts/secVMREAD Emulation Intercepts/sec]The rate of VMREAD instructions emulated while executing guest code on the virtual processor. VMREAD Emulation Intercepts Base VMREAD Emulation Intercepts BaseJThe total number of VMREAD instructions emulated on the virtual processor.!VMREAD Instruction Emulation Cost!VMREAD Instruction Emulation CostIThe average time (in nanoseconds) spent enumulating a VMREAD instruction. VMWRITE Emulation Intercepts/sec VMWRITE Emulation Intercepts/sec^The rate of VMWRITE instructions emulated while executing guest code on the virtual processor.!VMWRITE Emulation Intercepts Base!VMWRITE Emulation Intercepts BaseKThe total number of VMWRITE instructions emulated on the virtual processor."VMWRITE Instruction Emulation Cost"VMWRITE Instruction Emulation CostJThe average time (in nanoseconds) spent enumulating a VMWRITE instruction.VMXOFF Emulation Intercepts/secVMXOFF Emulation Intercepts/sec]The rate of VMXOFF instructions emulated while executing guest code on the virtual processor. VMXOFF Emulation Intercepts Base VMXOFF Emulation Intercepts BaseJThe total number of VMXOFF instructions emulated on the virtual processor.!VMXOFF Instruction Emulation Cost!VMXOFF Instruction Emulation CostIThe average time (in nanoseconds) spent enumulating a VMXOFF instruction.VMXON Emulation Intercepts/secVMXON Emulation Intercepts/sec\The rate of VMXON instructions emulated while executing guest code on the virtual processor.VMXON Emulation Intercepts BaseVMXON Emulation Intercepts BaseIThe total number of VMXON instructions emulated on the virtual processor. VMXON Instruction Emulation Cost VMXON Instruction Emulation CostHThe average time (in nanoseconds) spent enumulating a VMXON instruction.Nested VM Entries/secNested VM Entries/secRThe rate of nested VM entries while executing guest code on the virtual processor.Nested VM Entries BaseNested VM Entries Base?The total number of nested VM entries on the virtual processor.Nested VM Entries CostNested VM Entries CostEThe average time (in nanoseconds) spent processing a nested VM entry. Nested SLAT Soft Page Faults/sec Nested SLAT Soft Page Faults/sec]The rate of nested SLAT soft page faults while executing guest code on the virtual processor.!Nested SLAT Soft Page Faults Base!Nested SLAT Soft Page Faults BaseJThe total number of nested SLAT soft page faults on the virtual processor.!Nested SLAT Soft Page Faults Cost!Nested SLAT Soft Page Faults CostQThe average time (in nanoseconds) spent processing a nested SLAT soft page fault.PA Nested SLAT Hard Page Faults/sec Nested SLAT Hard Page Faults/sec]The rate of nested SLAT hard page faults while executing guest code on the virtual processor.!Nested SLAT Hard Page Faults Base!Nested SLAT Hard Page Faults BaseJThe total number of nested SLAT hard page faults on the virtual processor.!Nested SLAT Hard Page Faults Cost!Nested SLAT Hard Page Faults CostQThe average time (in nanoseconds) spent processing a nested SLAT hard page fault.+InvEpt All Context Emulation Intercepts/sec+InvEpt All Context Emulation Intercepts/seciThe rate of InvEpt All Context instructions emulated while executing guest code on the virtual processor.PA,InvEpt All Context Emulation Intercepts Base,InvEpt All Context Emulation Intercepts BaseVThe total number of InvEpt All Context instructions emulated on the virtual processor.-InvEpt All Context Instruction Emulation Cost-InvEpt All Context Instruction Emulation CostRThe average time (in nanoseconds) spent emulating an InvEpt All Context intercept..InvEpt Single Context Emulation Intercepts/sec.InvEpt Single Context Emulation Intercepts/seclThe rate of InvEpt Single Context instructions emulated while executing guest code on the virtual processor./InvEpt Single Context Emulation Intercepts Base/InvEpt Single Context Emulation Intercepts BaseYThe total number of InvEpt Single Context instructions emulated on the virtual processor.PA0InvEpt Single Context Instruction Emulation Cost0InvEpt Single Context Instruction Emulation CostUThe average time (in nanoseconds) spent emulating an InvEpt Single Context intercept.,InvVpid All Context Emulation Intercepts/sec,InvVpid All Context Emulation Intercepts/secjThe rate of InvVpid All Context instructions emulated while executing guest code on the virtual processor.-InvVpid All Context Emulation Intercepts Base-InvVpid All Context Emulation Intercepts BaseWThe total number of InvVpid All Context instructions emulated on the virtual processor..InvVpid All Context Instruction Emulation Cost.InvVpid All Context Instruction Emulation CostSThe average time (in nanoseconds) spent emulating an InvVpid All Context intercept.PA/InvVpid Single Context Emulation Intercepts/sec/InvVpid Single Context Emulation Intercepts/secmThe rate of InvVpid Single Context instructions emulated while executing guest code on the virtual processor.0InvVpid Single Context Emulation Intercepts Base0InvVpid Single Context Emulation Intercepts BaseZThe total number of InvVpid Single Context instructions emulated on the virtual processor.1InvVpid Single Context Instruction Emulation Cost1InvVpid Single Context Instruction Emulation CostVThe average time (in nanoseconds) spent emulating an InvVpid Single Context intercept./InvVpid Single Address Emulation Intercepts/sec/InvVpid Single Address Emulation Intercepts/secmThe rate of InvVpid Single Address instructions emulated while executing guest code on the virtual processor.0InvVpid Single Address Emulation Intercepts Base0InvVpid Single Address Emulation Intercepts BaseZThe total number of InvVpid Single Address instructions emulated on the virtual processor.1InvVpid Single Address Instruction Emulation Cost1InvVpid Single Address Instruction Emulation CostVThe average time (in nanoseconds) spent emulating an InvVpid Single Address intercept.&Nested TLB Page Table Reclamations/sec&Nested TLB Page Table Reclamations/secCThe rate of reclamations of unlinked page tables in the nested TLB.#Nested TLB Page Table Evictions/sec#Nested TLB Page Table Evictions/sec3The rate of page table evictions in the nested TLB.+Flush Physical Address Space Hypercalls/sec+Flush Physical Address Space Hypercalls/secoThe rate of Flush Guest Physical Adress Space hypercalls made by the guest hypervisor on the virtual processor.*Flush Physical Address List Hypercalls/sec*Flush Physical Address List Hypercalls/secoThe rate of Flush Guest Physical Address List hypercalls made by the guest hypervisor on the virtual processor."Posted Interrupt Notifications/sec"Posted Interrupt Notifications/secDThe rate of posted interrupt notifications on the virtual processor.Posted Interrupt Scans/secPosted Interrupt Scans/sec?The rate of posted interrupt scanning on the virtual processor.PATotal Core Run TimeTotal Core Run Time�The total time (in 100ns) spent by any virtual processor in the same virtual core in guest and hypervisor code for SMT enabled guests.Guest Idle TimeGuest Idle Time-The total time (in 100ns) the guest was idle.$HWP Request MSR Context Switches/sec$HWP Request MSR Context Switches/sec8The rate of hypervisor HWP_REQUEST MSR context switches.CPU Wait Time Bucket 0CPU Wait Time Bucket 0cLess than 409.6 us spent waiting for a virtual processor to be dispatched onto a logical processor.CPU Wait Time Bucket 1CPU Wait Time Bucket 1d409.6 us - 819.1 us spent waiting for a virtual processor to be dispatched onto a logical processor.CPU Wait Time Bucket 2CPU Wait Time Bucket 2e819.2 us - 1.6383 ms spent waiting for a virtual processor to be dispatched onto a logical processor.CPU Wait Time Bucket 3CPU Wait Time Bucket 3f1.6384 ms - 3.2766 ms spent waiting for a virtual processor to be dispatched onto a logical processor.CPU Wait Time Bucket 4CPU Wait Time Bucket 4f3.2768 ms - 6.5535 ms spent waiting for a virtual processor to be dispatched onto a logical processor.PACPU Wait Time Bucket 5CPU Wait Time Bucket 5g6.5536 ms - 13.1071 ms spent waiting for a virtual processor to be dispatched onto a logical processor.CPU Wait Time Bucket 6CPU Wait Time Bucket 6hGreater than 13.1071 ms spent waiting for a virtual processor to be dispatched onto a logical processor.VMLOAD Emulation Intercepts/secVMLOAD Emulation Intercepts/sec]The rate of VMLOAD instructions emulated while executing guest code on the virtual processor. VMLOAD Emulation Intercepts Base VMLOAD Emulation Intercepts BaseJThe total number of VMLOAD instructions emulated on the virtual processor.!VMLOAD Instruction Emulation Cost!VMLOAD Instruction Emulation CostGThe average time (in nanoseconds) spent emulating a VMLOAD instruction.VMSAVE Emulation Intercepts/secVMSAVE Emulation Intercepts/sec]The rate of VMSAVE instructions emulated while executing guest code on the virtual processor. VMSAVE Emulation Intercepts Base VMSAVE Emulation Intercepts BaseJThe total number of VMSAVE instructions emulated on the virtual processor.!VMSAVE Instruction Emulation Cost!VMSAVE Instruction Emulation CostGThe average time (in nanoseconds) spent emulating a VMSAVE instruction.PA(GIF Instruction Emulation Intercepts/sec(GIF Instruction Emulation Intercepts/sec`The rate of STGI/CLGI instructions emulated while executing guest code on the virtual processor.)GIF Instruction Emulation Intercepts Base)GIF Instruction Emulation Intercepts BaseMThe total number of STGI/CLGI instructions emulated on the virtual processor.GIF Instruction Emulation CostGIF Instruction Emulation CostKThe average time (in nanoseconds) spent emulating a GIF access instruction.#Emulated errata SVM instruction/sec#Emulated errata SVM instruction/sec4The rate of SVM instructions emulated due to errata.
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Placeholder 9Placeholder counter.Placeholder 10Placeholder 10Placeholder counter.Guest Run TimeGuest Run TimeGThe total time (in 100ns) spent by the virtual processor in guest code.% Total Run Time% Total Run TimeSThe percentage of time spent by the virtual processor in guest and hypervisor code.% Hypervisor Run Time% Hypervisor Run TimeIThe percentage of time spent by the virtual processor in hypervisor code.% Guest Run Time% Guest Run TimeDThe percentage of time spent by the virtual processor in guest code.% Guest Idle Time% Guest Idle TimeYThe percentage of time spent by the virtual processor in an idle state due to guest code.% Total Core Run Time% Total Core Run Time�The percentage of time spent by any virtual processor in the same virtual core in guest and hypervisor code for SMT enabled guests.PATotal Messages/secTotal Messages/sec8The rate of total messages sent to the parent partition.Total Intercepts BaseTotal Intercepts Base:The total count of all the hypervisor intercepts messages.Total Intercepts/secTotal Intercepts/sec+The rate of hypervisor intercepts messages.Total Intercepts CostTotal Intercepts CostHThe average time (in nanoseconds) spent handling a hypervisor intercept.PA% Remote Run Time% Remote Run TimeOThe percentage of time spent by the virtual processor running on a remote node./Total Virtualization Instructions Emulated Base/Total Virtualization Instructions Emulated BaseQThe total count of virtualization instructions emulated on the virtual processor..Total Virtualization Instructions Emulated/sec.Total Virtualization Instructions Emulated/sec1The rate of virtualization instructions emulated.0Total Virtualization Instructions Emulation Cost0Total Virtualization Instructions Emulation CostYThe average time (in nanoseconds) spent emulating a virtualization extension instruction.Global Reference TimeGlobal Reference TimejA constant rate time source that is used as by a number of performance counters for duration calculations.	Ideal Cpu	Ideal CpuDThe index of the ideal logical processor for this virtual processor.Scheduling PriorityScheduling Priority>The configured scheduling priority for this virtual processor.RDPMC Instructions/secRDPMC Instructions/secOThe rate of RDPMC instructions executed by guest code on the virtual processor.PARDPMC Instructions BaseRDPMC Instructions BaseWThe total number of RDPMC instructions executed by guest code on the virtual processor.RDPMC Instructions CostRDPMC Instructions CostHThe average time (in nanoseconds) spent processing an RDPMC instruction.,Performance Monitoring vPMU MSR Accesses/sec,Performance Monitoring vPMU MSR Accesses/secNThe rate of intercepted accesses to vPMU related MSRs on this virtual procesor-Performance Monitoring vPMU MSR Accesses Base-Performance Monitoring vPMU MSR Accesses BaseXThe total number of intercepted accesses to vPMU related MSRs on this virtual processor.PA+Performance Monitoring LBR MSR Accesses/sec+Performance Monitoring LBR MSR Accesses/secMThe rate of intercepted accesses to LBR related MSRs on this virtual procesor,Performance Monitoring LBR MSR Accesses Base,Performance Monitoring LBR MSR Accesses BaseWThe total number of intercepted accesses to LBR related MSRs on this virtual processor.+Performance Monitoring IPT MSR Accesses/sec+Performance Monitoring IPT MSR Accesses/secMThe rate of intercepted accesses to IPT related MSRs on this virtual procesor,Performance Monitoring IPT MSR Accesses Base,Performance Monitoring IPT MSR Accesses BaseWThe total number of intercepted accesses to IPT related MSRs on this virtual processor.%Performance Monitoring Interrupts/sec%Performance Monitoring Interrupts/secPThe rate of performance monitoring interrupts forwarded to this virtual procesor&Performance Monitoring Interrupts Base&Performance Monitoring Interrupts BaseZThe total number of performance monitoring interrupts forwarded to this virtual processor.�4VS_VERSION_INFO��
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